1. Field of the Invention
The present invention relates generally to a drive circuit suited for use in a large-scale semiconductor integrated circuit, and more particularly to a drive circuit capable of performing a high-speed switching in compliance with a synchronizing signal.
2. Description of the Prior Art
A drive circuit for performing a switching operation in synchronization with a clock signal generally comprises a number of drive circuit elements and is used, for example, on word lines of RAMs, ROMs, and register files or on output lines for AND signals of PLAs.
FIG. 1 depicts a conventional drive circuit element comprising a NAND circuit 901, an inverter 902, an input line 911 of an input signal AD, an input line 912 of a clock signal PH, and an output line 913 of an output WL from the drive circuit element. A CMOS circuit, a BiCMOS circuit, a BiNMOS circuit, or the like is preferably employed as the inverter 902.
FIG. 2 depicts another conventional drive circuit element employing a P-channel MOSFET 903 and two N-channel MOSFETs 904 and 905. An input line 914 of an inverted ADDRESS signal AD is connected to a gate of the P-channel MOSFET 903 and to that of the N-channel MOSFET 904. When a clock signal PH is at a high level, the P-channel MOSFET 903 raises the voltage of an output line 913. When an ADDRESS signal AD is at a low level, i.e, an inverted ADDRESS signal AD is at a high level, the N-channel MOSFET 904 lowers the voltage of the output line 913. When the clock signal PH is at a low level, i.e., an inverted clock signal PH is at a high level, the N-channel MOSFET 905 lowers the voltage of the output line 913.
When these conventional drive circuit elements are employed to drive word lines of a large-scale RAM, the problem of lowering the switching speed occurs.
In the drive circuit element shown in FIG. 1, for example, let the case be considered in which the input signal AD is a decoded output of a line address and the clock signal PH is a synchronizing signal. The clock signal PH is required to drive both the gate of the N-channel MOSFET and that of the P-channel MOSFET of the NAND circuit 901. In a RAM having a large line size, because a number of drive circuit elements are connected to a clock signal line, a load capacitance Cph of the input signal line becomes large, thereby lowering the switching speed.
On the other hand, in the drive circuit element shown in FIG. 2, the input line of the clock signal PH is connected to a source of the P-channel MOSFET. As viewed from a clock output circuit, a load connected to the output line is driven via a internal resistance of the P-channel MOSFET during the ON-state thereof. Because the word lines of a RAM have respective relatively large loads on output lines thereof, the presence of this resistance lowers the switching speed.
Due to the high speed of N-channel MOSFETs, the retardation of the short channel effect of P-channel MOSFETs, the matching with the NMOS process, and the like, the so-called N-well method, in which a P-channel MOSFET is formed in a N-type impurity range formed on a P-type substrate, is generally employed as a device formation method. Because the N-well is higher in impurity concentration than the P-type substrate, the junction capacitance of the P-channel MOSFET between the N-well and the source or between the N-well and the drain is greater than that of the N-channel MOSFET. When a number of drive circuit elements are connected to the clock signal line, the load capacitance Cph becomes large, and therefore, the switching speed is lowered. Furthermore, because the drain saturation current of the P-channel MOSFET is less than that of the N-channel MOSFET, the gate size of the P-channel MOSFET must be enlarged for the high-speed switching operation. This conversely further increases the junction capacitance.